18#if defined(_MSC_VER) && (defined(_M_IX86) || defined(_M_AMD64))
20void getCpuId(uint32_t array[4], uint32_t nInfoType)
22 __cpuid(
reinterpret_cast<int*
>(array), nInfoType);
24#elif (defined(__i386__) || defined(__x86_64__))
26void getCpuId(uint32_t array[4], uint32_t nInfoType)
28 __cpuid_count(nInfoType, 0, *(array + 0), *(array + 1), *(array + 2), *(array + 3));
31void getCpuId(uint32_t array[4], uint32_t )
33 array[0] = array[1] = array[2] = array[3] = 0;
38bool checkAVXSupportInOS()
41#if defined(_MSC_VER) && (defined(_M_IX86) || defined(_M_AMD64))
42 xcr0 = uint32_t(_xgetbv(0));
43#elif (defined(__i386__) || defined(__x86_64__))
44 __asm__(
"xgetbv" :
"=a"(xcr0) :
"c"(0) :
"%edx");
46 return ((xcr0 & 6) == 6);
51#define HYPER_bit (1 << 28)
52#define SSE2_bit (1 << 26)
53#define SSSE3_bit (1 << 9)
54#define SSE41_bit (1 << 19)
55#define SSE42_bit (1 << 20)
56#define XSAVE_bit (1 << 27)
57#define AVX_bit (1 << 28)
58#define AVX2_bit (1 << 5)
59#define AVX512F_bit (1 << 16)
65 uint32_t info[] = { 0, 0, 0, 0 };
71 uint32_t aCpuInfoArray[] = { 0, 0, 0, 0 };
72 getCpuId(aCpuInfoArray, 1);
77 if ((aCpuInfoArray[3] &
SSE2_bit) != 0)
89 if (((aCpuInfoArray[2] &
AVX_bit) != 0) && ((aCpuInfoArray[2] &
XSAVE_bit) != 0))
91 if (checkAVXSupportInOS())
97 uint32_t aExtendedInfo[] = { 0, 0, 0, 0 };
98 getCpuId(aExtendedInfo, 7);
100 if ((aExtendedInfo[1] &
AVX2_bit) != 0)
109 return eInstructions;
115 return (eCPUFlags & eInstructions) == eInstructions;
126 aString +=
"SSE4.1 ";
128 aString +=
"SSE4.2 ";
134 aString +=
"AVX512F ";
register sal_uInt32 r28 __asm__("%r28")
OUString instructionSetSupportedString()
Returns a string of supported instructions.
bool isCpuInstructionSetSupported(InstructionSetFlags eInstructions)
Check if a certain instruction set is supported by the CPU at runtime.
InstructionSetFlags getCpuInstructionSetFlags()
Get supported instruction set flags determined at runtime by probing the CPU.